1. Field of the Invention
The present invention relates to a mobile communication system. More particularly, the present invention relates to an apparatus and method for controlling an interleaver/deinterleaver memory in a mobile communication system.
2. Description of the Related Art
Mobile communication systems that provide a circuit-based voice service are classified into one of a Frequency Division Multiple Access (FDMA) scheme, Time Division Multiple Access (TDMA) scheme, and Code Division Multiple Access (CDMA) scheme. In the FDMA scheme, a predetermined frequency band is divided into multiple channels with each subscriber being allocated their own frequency channel. In the TDMA scheme, a frequency channel is shared by multiple subscribers with each subscriber being allocated their own time band. In the CDMA scheme, a frequency band and time band is shared by multiple subscribers with each subscriber being allocated their own allocated codes.
With the evolution of communication technologies, mobile communication systems now provide a fast packet data service, which can provide a mobile terminal with not only a conventional voice communication service but also with multimedia services such as e-mail, a still image and a motion image.
Third-generation (3G) mobile communication systems support both conventional voice services and packet services. Exemplary 3G mobile communication systems include synchronous CDMA 2000 1x and 1x Evolution Data Only (1x EV-DO), Evolution of Data and Voice (EV-DV) for supporting high-speed packet transmission and asynchronous Universal Mobile Telecommunications Systems (UMTS).
When a digital signal is transmitted in a mobile communication system, a conventional Viterbi or Reed-Solomon (RS) decoder has excellent error correction capability. However, it is difficult for the decoder to correct continuously occurring burst errors of more than a predetermined size. To address this disadvantage, an interleaver/deinterleaver permutes input signals, thereby distributing the burst errors. Thereby, the decoder can efficiently correct the errors.
FIG. 1A illustrates a structure of a digital transmitter/receiver using a conventional interleaver/deinterleaver and FIG. 1B illustrates exemplary signals from the conventional interleaver/deinterleaver of FIG. 1A.
Referring to FIG. 1A, an encoder 110 of the transmitter attaches additional information to signals or varies a signal form for error correction by the receiver. In FIG. 1B, reference numeral 105 denotes signals encoded by the encoder 110. An interleaver 120 permutes the encoded signals 105. In FIG. 1B, reference numeral 106 denotes signals permuted by the interleaver 120. After passing through the interleaver 120, the signals 106 are affected by an external error or noise and therefore three consecutive errors occur in A1, A14, and A11 as indicated by reference numeral 107. If the number of burst errors capable of being corrected in an encoder/decoder 140 is two, the three consecutive errors cannot be properly corrected. When an interleaver/deinterleaver 130 of the receiver restores the original order of the signals, distorted signals are distributed as indicated by reference numeral 108, such that the decoder 140 can properly correct errors.
FIG. 2 illustrates a structure of the conventional deinterleaver.
The deinterleaver 130 includes a write address generator 220 for generating an address at which an input signal is recorded, a memory 210 for storing the input signal, and a read address generator 230 for generating an address from which data is read on the basis of a deinterleaving rule.
The input signal is sequentially recorded in the memory 210. A valid storage area is set according to the size of a received packet. A start address of the valid storage area is defined as ST_ADDR and an end address is defined as END_ADDR. The write address generator 220 sequentially increments a write address value WD_ADDR by one whenever the input signal is received. When WD_ADDR is more than END_ADDR, WD_ADDR is reset to ST_ADDR, i.e., WD_ADDR=ST_ADDR.
Because a newly received packet is conventionally accumulated and recorded in content at an address WD_ADDR designated by the write address generator 220, a memory write operation by a controller (not illustrated) is simple. When reception of a packet is completed, the controller should erase all content elements of an interleaver/deinterleaver memory at a predetermined time for the next packet reception. However, because a memory erasure is an operation for recording “0” at valid memory addresses, i.e., all memory addresses ranging from ST_ADDR to END_ADDR, time and power are required to access all valid addresses and record “0” at the accessed addresses.
When a size of a packet to be subsequently received is less than that of a packet whose reception is completed, it is advantageous to erase only part of a memory area rather than a total memory area in terms of time and power.
On the other hand, when the size of the packet to be subsequently received is more than that of the packet whose reception is completed, it is advantageous to erase only a memory area used by the completely received packet rather than the total memory area in terms of time and power.
However, the size of the packet to be subsequently received cannot be detected in advance. For this reason, the controller conventionally erases the memory area used by the completely received packet or the total memory area, resulting in unnecessary time and power consumption.
Further, when a time interval between the completely received packet and the packet to be subsequently received is shorter than the memory erasure time, it is difficult to apply a deinterleaving operation.
Accordingly, there is a need for an improved apparatus and method for controlling an interleaver/deinterleaver memory in a mobile communication system.